S-1701 Datasheet, PDF (42/70 Pages) Seiko Instruments Inc – HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR WITH RESET FUNCTION

HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR WITH RESET FUNCTION
S-1701 Series
Rev.2.4_00
Detector block
1. Basic operation
Figure 36 shows a block diagram of the detector block.
V_IN V_SENSE
Current
supply
R_a
+
−
R_b
V_ref
R_c
Delay circuit
Nch
N1
V_SS
*1. Parasitic diode
VDOUT
*1
Figure 36 Block Diagram (Detector Block)
(1) When the SENSE voltage (V_SENSE) is higher than the release voltage (+V_DET), the Nch
transistor is OFF and V_IN (high) is output. Since the Nch transistor N1 in Figure 36 is OFF,
the comparator input voltage is
(R_b +
R_a
R_c) •
+ R_b
V_SENSE
+ R_c
.
(2) When V_SENSE goes below +V_DET, V_IN is output, as long as V_SENSE remains above the detection
voltage (−V_DET). When the V_SENSE falls below −V_DET, the Nch transistor becomes ON and V_SS is
output. At this time, the Nch transistor N1 in Figure 36
becomes ON, and the comparator input voltage is changed to ^{Rb • VSENSE} .
R_a + R_b
(3) When V_IN falls below the minimum operating voltage, the output becomes undefined. In this
case the output becomes V_IN because it is pulled up.
(4) V_SS is output when V_IN rises above the minimum operating voltage. The V_SS level still appears
even when V_SENSE surpasses −V_DET, as long as it does not exceed the release voltage +V_DET.
When V_SENSE rises above +V_DET, the Nch transistor becomes OFF and V_IN is output. V_IN at the
VDOUT pin is delayed for t_D due to the delay circuit.
(5) In the S-1701 Series, the detection voltage can be set within the range of 1.5 to 5.5 V
(operating voltage range: 0.8 to 6.5 V).
42
Seiko Instruments Inc.