S-1701 Datasheet, PDF (37/70 Pages) Seiko Instruments Inc – HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR WITH RESET FUNCTION

HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR WITH RESET FUNCTION
Rev.2.4_00
S-1701 Series
2. Hysteresis width (V_HYS)
The hysteresis width is the voltage difference between the detection voltage and the release voltage.
The existence of the hysteresis width prevents malfunction caused by noise on the input voltage.
3. Delay time (t_D)
The delay time is a time internally measured from the instant at which the voltage input to the VDD pin
exceeds the release voltage (+V_DET) to the point at which the output of the OUT pin inverts.
S-1701 Series A/ D/ G/ K/ N/ R/ U/ X types:
No delay (60 µs typ.)
S-1701 Series B/ E/ H/ L/ P/ S/ V/ Y types:
50 ms typ.
S-1701 Series C/ F/ J/ M/ Q/ T/ W/ Z types:
100 ms typ.
V
+V_DET
V_IN or
V_SENSE
When t_D = 60 µs
When t_D = 50 ms, 100 ms
V_DOUT
t_D
t_D
Remark The figure shows the case when the SENSE pin is connected to VIN.
Figure 31
4. Through-type current
The through-type current refers to the current that flows instantaneously when the voltage detector
detects and releases a voltage. The through-type current flows at a frequency of 20 kHz during the
release delay time since the internal logic circuit operates.
Seiko Instruments Inc.
37