C501_1 Datasheet, PDF (85/121 Pages) Siemens Semiconductor Group – 8-Bit Single-Chip Microcontroller

Interrupt System
C501
7.2 Interrupt Priority Level Structure
A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-
priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source.
If two requests of different priority level are received simultaneously, the request of higher priority is
serviced. If requests of the same priority are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority
structure determined by the polling sequence as shown in table 7-8 below:
Table 7-8
Priority-within-Level Structure
Interrupt Source
External Interrupt 0,
Timer 0 Interrupt,
External Interrupt 1,
Timer 1 Interrupt,
Serial Channel,
Timer 2 Interrupt,
IE0
TF0
IE1
TF1
RI or TI
TF2 or EXF2
Priority
High
↓
Low
Semiconductor Group
7-7