C501_1 Datasheet, PDF (83/121 Pages) Siemens Semiconductor Group – 8-Bit Single-Chip Microcontroller

Interrupt System
C501
The timer 2 interrupt is generated by the logical OR of bit TF2 and EXF2 in register T2CON.
Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the
service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and
the bit will have to be cleared by software.
The serial port interrupt is generated by a logical OR of flag RI and TI in SFR SCON. Neither of
these flags is cleared by hardware when the service routine is vectored too. In fact, the service
routine will normally have to determine whether it was the receive interrupt flag or the transmission
interrupt flag that generated the interrupt, and the bit will have to be cleared by software.
Special Function Register T2CON (Address C8H)
Special Function Register SCON (Address. 98H)
Reset Value : 00H
Reset Value : 00H
Bit No.
C8H
MSB
CF_H
TF2
CE_H CD_H CC_H CB_H
EXF2 RCLK TCLK EXEN2
CA_H
TR2
LSB
C9_H C8_H
C/T2 CP/RL2
T2CON
Bit No. 9F_H 9E_H 9D_H 9C_H 9B_H 9A_H 99_H
98H SM0 SM1 SM2 REN TB8 RB8 TI
98_H
RI SCON
Bit
TF2
EXF2
TI
RI
The shaded bits are not used for interrupt request control.
Function
Timer 2 Overflow Flag.
Set by a timer 2 overflow. Must be cleared by software. TF2 will not be set when
either RCLK = 1 or TCLK = 1.
Timer 2 External Flag.
Set when either a capture or reload is caused by a negative transition on T2EX and
EXEN2 = 1. When timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to
vector to the timer 2 interrupt routine. EXF2 must be cleared by software. EXF2
does not cause an interrupt in up/down counter mode (DCEN = 1, SFR T2MOD)
Serial interface transmitter interrupt flag
Set by hardware at the end of a serial data transmission. Must be cleared by
software.
Serial interface receiver interrupt flag
Set by hardware if a serial data byte has been received. Must be cleared by
software.
Semiconductor Group
7-5