C501_1 Datasheet, PDF (34/121 Pages) Siemens Semiconductor Group – 8-Bit Single-Chip Microcontroller

System Reset
C501
5.2 Hardware Reset Timing
This section describes the timing of the hardware reset signal.
The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase 2.
Thus, the external reset signal is synchronized to the internal CPU timing. When the reset is found
active (high level) the internal reset procedure is started. It needs two complete machine cycles to
put the complete device to its correct reset state, i.e. all special function registers contain their
default values, the port latches contain 1’s etc. The RESET signal must be active for at least two
machine cycles; after this time the C501 remains in its reset state as long as the signal is active.
When the signal goes inactive this transition is recognized in the following state 5 phase 2 of the
machine cycle. Then the processor starts its address output (when configured for external ROM) in
the following state 5 phase 1. One phase later (state 5 phase 2) the first falling edge at pin ALE
occurs.
Figure 5-3 shows this timing for a configuration with EA = 0 (external program memory). Thus,
between the release of the RESET signal and the first falling edge at ALE there is a time period of
at least one machine cycle but less than two machine cycles.
One Machine Cycle
S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2
P1 P2
RESET
P0
P2
ALE
PCL
Inst. PCL
OUT
in OUT
PCH
PCH
OUT
OUT
MCT02092
Figure 5-3
CPU Timing after Reset
Semiconductor Group
5-2