C501_1 Datasheet, PDF (36/121 Pages) Siemens Semiconductor Group – 8-Bit Single-Chip Microcontroller

On-Chip Peripheral Components
C501
Figure 6-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each
of the 4 I/O-ports. The bit latch (one bit in the port’s SFR) is represented as a type-D flip-flop, which
will clock in a value from the internal bus in response to a “write-to-latch” signal from the CPU. The
Q output of the flip-flop is placed on the internal bus in response to a “read-latch” signal from the
CPU. The level of the port pin itself is placed on the internal bus in response to a “read-pin” signal
from the CPU. Some instructions that read from a port (i.e. from the corresponding port SFR P0 to
P3) activate the “read-latch” signal, while others activate the “read-pin” signal.
Read
Latch
Int. Bus
Write
to
Latch
Q
D
Port
Latch
Q
CLK
Port
Driver
Circuit
Port
Pin
Read
Pin
Figure 6-4
Basic Structure of a Port Circuitry
MCS01822
Semiconductor Group
6-2