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HYB514800BJ Datasheet, PDF (10/22 Pages) Siemens Semiconductor Group – 512kx8-Bit Dynamic RAM
HYB 514800BJ -60/-70/-80
512k x 8 DRAM
Notes:
1) All voltages are referenced to VSS
2) ICC1 , ICC3 , ICC4 and ICC6 depend on cycle rate.
3) ICC1 , ICC4 depend on output loading.
4) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,
a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
5) Vih (min.) and Vil (max.) are reference levels for measuring timing of input signals. Transition times are also
measured between Vih and Vil .
6) Measured with a load equivalent to 2 TTL loads and 100 pF.
7) toff (max.), tOEZ (max.) defines the time at which the output achieves the open-circuit conditions and are not
referenced to output voltage levels.
8) Either tRCH or tRRH must be satisfied for a read cycle.
9) These parameters are references to the CAS leading edge in early write and to the WRITE leading edge in
read-write cycles.
10) tWCS , tRWD , tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only.
If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance)
through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.) and tAWD > tAWD (min.), the cycle is a read-
write cycle and I/O will contain data read from the selected cell. If neither of the above sets of conditions is
satisfied, the condition of I/O (at access time) is indeterminate.
11) Operation within the tRCD (max.) limit ensure that tRAC (max.) can be met. tRCD (max.) is specified as a
reference point only. If tRAD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC .
12) Operation within the tRAD (max.) limit ensured that tRAC (max.) can be met. tRAD (max.) is specified as a
reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA .
13) AC measurements assume tT = 5 ns.
14) Either tDZC or tDZO must be satisfied.
15) Either tCDD or tODD must be satisfied.
Semiconductor Group
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