GS2962 Datasheet, PDF (63/82 Pages) Gennum Corporation – Integrated Narrow-Bandwidth PLL

4.11.2 Data Read or Write Access
Serial data is transmitted or received MSB first synchronous with the rising edge of the
Serial Clock, SCLK. The Chip Select (CS) signal must be active LOW a minimum of 1.5ns
(t0 in Figure 4-24) before the first clock edge to ensure proper operation.
During a Read sequence (Command Word R/W bit set HIGH), a wait state of 148ns (4 x
1/fPCLK, t5 in Figure 4-24) is required between writing the Command Word and reading
the following Data Word. The read bits are clocked out on the negative edges of SCLK.
NOTE 1: Where several devices are connected to the GSPI chain, only one CS_TMS may
be asserted during a read sequence.
During a Write sequence (Command Word R/W bit set LOW), a wait state of 37ns (1 x
1/fPCLK, t4 in Figure 4-24) is required between the Command Word and the following
Data Word. This wait state must also be maintained between successive Command
Word/Data Word write sequences. When Auto-increment mode is selected (AutoInc =
1), the wait state must be maintained between successive Data Words after the initial
Command Word/Data Word sequence.
During the write sequence, all command and following Data Words input at the SDIN
pin are output at the SDOUT pin as is.
When several devices are connected to the GSPI chain, data can be written
simultaneously to all the devices which have CS set LOW.
NOTE 2: If the application interface performs a Read or Write access after power-up,
prior to the application of a valid serial video input signal, the SCLK frequency must not
exceed 10MHz.
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 4-23: Data Word Format
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Data Sheet
48005 - 7
October 2010
63 of 82