GS2962 Datasheet, PDF (30/82 Pages) Gennum Corporation – Integrated Narrow-Bandwidth PLL

The input data width is controlled by the setting of the 20BIT/10BIT pin as shown in
Table 4-2 above.
NOTE: When in HD 10-bit mode, asserting the SMPTE_BYPASS LOW to put the device
in SMPTE-BYPASS mode will create video errors. If the user desires to use the device as
a simple serializer in HD 10-bit mode, all video processing features may be disabled by
setting the IOPROC_EN/DIS pin LOW.
4.2.4 Parallel Input Clock (PCLK)
The frequency of the PCLK input signal of the GS2962 is determined by the input data
format and operating mode selection.
Table 4-3 below lists the input PCLK rates and input signal formats according to the
external selection pins for the GS2962.
Table 4-3: GS2962 PCLK Input Rates
Input Data Format
20BIT/10BIT
20-bit demultiplexed
3G format
20-bit demultiplexed
HD format
20-bit data Input
3G format
20-bit data input
HD format
20-bit demultiplexed
SD format
20-bit data input
SD format
10-bit multiplexed
3G DDR format
10-bit multiplexed
HD format
10-bit data input
HD format
10-bit multiplexed
SD format
10-bit data input
SD format
10-bit ASI input
SD format
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
Pin Settings
RATE_
SEL0
LOW
RATE_
SEL1
HIGH
SMPTE_
BYPASS
HIGH
LOW
LOW
HIGH
LOW
HIGH
LOW
LOW
LOW
LOW
HIGH
X
HIGH
HIGH
X
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
LOW
LOW
LOW
HIGH
X
HIGH
HIGH
X
LOW
HIGH
X
LOW
DVB-ASI
PCLK Rate
X
X
LOW
LOW
LOW
LOW
LOW
LOW
LOW
X
LOW
HIGH
148.5 or 148.5/1.001MHz
74.25 or 74.25/1.001MHz
148.5 or 148.5/1.001MHz
74.25 or 74.25/1.001MHz
13.5MHz
13.5MHz
148.5 or 148.5/1.001MHz
148.5 or 148.5/1.001MHz
148.5 or 148.5/1.001MHz
27MHz
27MHz
27MHz
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Data Sheet
48005 - 7
October 2010
30 of 82