LC89052T Datasheet, PDF (40/42 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89052T
DO7
0
0
8
Address
16
Track
24
Index
32
Minute
40
Second
48
Frame
56
Zero
64
abs minute
72
abs second
80
abs frame
Table 9.12 Output Register: Sub-code Q Data with CRC Flag (0xED)
DO6
DO5
DO4
DO3
DO2
DO1
0
0
0
0
0
CRC
Address
Address
Address
Control
Control
Control
Track
Track
Track
Track
Track
Track
Index
Index
Index
Index
Index
Index
Minute
Minute
Minute
Minute
Minute
Minute
Second
Second
Second
Second
Second
Second
Frame
Frame
Frame
Frame
Frame
Frame
Zero
Zero
Zero
Zero
Zero
Zero
abs minute
abs minute
abs minute
abs minute
abs minute
abs minute
abs second
abs second
abs second
abs second
abs second
abs second
abs frame
abs frame
abs frame
abs frame
abs frame
abs frame
DO0
CRC
Control
Track
Index
Minute
Second
Frame
Zero
abs minute
abs second
abs frame
• When sub-code Q data is included in the input data, this data can be read together with the CRC calculation result.
• To read the sub-code Q data, E/INT must be set to be selected as an interrupt output so that the sub-code Q data
readout load signal can be output.
• When sub-code Q data is detected, the E/INT signal outputs a high level or a high-level pulse. The sub-code Q data is
updated on each rising edge of the E/INT signal. The readout must be completed within 13.3ms (standard speed) or
6.6ms (2× speed), starting at the E/INT rising edge.
• The cyclic redundancy code (CRC) is a set of flags that decide whether the 80 bits of sub-code Q data is correct. Note
that the same data is loaded into both the DO0 and DO1 CRC flags.
CRC
Low
High
Table 9.13 CRC Flag Output
Output conditions
Errors are found in the sub-code Q data.
The sub-code Q data is correct.
No.7457-40/42