LC89052T Datasheet, PDF (23/42 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89052T
8.5.6 Processing during error recovery
• When the preambles B, M, and W are detected, the PLL circuit goes to the locked state and data demodulation starts.
• The DATAO output data is output on the first LRCK edge after ERROR goes low.
15 ms to 50 ms
ERROR
Internal clock signal
OK
LRCK
DATAO
data
Output starts at the LRCK edge immediately following the fall of the ERROR flag.
Figure 8.11 Data Processing when Data Demodulation Starts
8.6 Channel Status Data Output_{______________}
8._{_}6_{__}._{_}1_{____}D_{___}a_{__}t_{_}a delimiter bit 1 output ( AUDIO )
• AUDIO outputs channel status bit 1, which indicates whether or not the input bi-phase data is PCM audio data.
______
AUDIO pin
Low
High
______________
Table 8.10 AUDIO Output
Output conditions
PCM audio data (CS bit 1 = low)
Non-PCM data (CS bit 1 = high)
8.6.2 Emphasis information output (E/INT)
• E/INT is shared by the microcontroller interface interrupt function. However, in the initial state, it outputs the
presence or absence of emphasis with a time constant of 50/15µs for use in consumer products or broadcast studios.
E/INT pin
Low
High
Table 8.11 E/INT Output
Output conditions
No pre-emphasis
50/15µs pre-emphasis
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