LC89052T Datasheet, PDF (18/42 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89052T
8.4.4 Output data formats: special mode (DATAO)
• The output format of after-demodulation audio data must be set with OFSEL[2:0].
• In the format shown below, input data information except the audio data is output as well.
• BCK, LRCK, and DATAO are output in synchronization with the rising edge of CKOUT. DATAO is output in
synchronization with the falling edge of BCK.
• Generation of output data starts at the LRCK edge immediately after the ERROR output turns low.
• (3) as bi-phase data output, the input bi-phase data is output in synchronization with 128fs clock BCK and fs clock
LRCK. However, BCK in PLL unlocked state is set to the 64fs clock.
• As for NRZ data output in (4), (5), 28bits are output. 4 bits of validity (V), user data (U), channel status (C) and also
preamble B (Z) plus 24 bits of LSB first audio data. H is output as Z bit in the frames (L-ch and R-ch) whose
preamble B is confirmed.
• The low level is output all the time except for the effective bit length of the NRZ data output.
LRCK
BCK
DATAO ^{C P}
R-ch
L-ch
LSB
MSB V U C P
LSB
MSB V U C P
(3) : Biphase data output (OFSEL[2 : 0]=101)
LRCK
BCK
DATAO
L-ch
R-ch
LSB -24 bit- MSB V U C Z
LSB -24 bit- MSB V U C Z
28 bits
28 bits _{Notice : "Z" means Preamble "B"}
(4) : NRZ data I²S output (OFSEL[2 : 0]=110)
LRCK
BCK
DATAO
R-ch
L-ch
LSB -24 bit- MSB V U C Z
LSB -24 bit- MSB V U C Z
28 bits
28 bits
Notice : "Z" means Preamble "B"
(5) : NRZ data LSB first left-justified output (OFSEL[2 : 0]=111)
Figure 8.7 Data Output Timing (Special Mode)
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