LC89052T Datasheet, PDF (31/42 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

9.6.2 Details of write data
LC89052T
DI7
MCKHFO
DI15
XISEL3
Table 9.5 Input Register Function Settings 1: System Settings (0xE8)
DI6
DI5
DI4
DI3
DI2
DI1
PLLCK1
PLLCK0
PLLOPR
PDOWN1
PDOWN0
0
DI14
DI13
DI12
DI11
DI10
DI9
XISEL2
XISEL1
XISEL0
OCKSEL
AMPCNT
AMPOPR
DI0
SYSRST
DI8
0
SYSRST:
System reset
0: No reset performed (initial value)
1: Reset all circuits other than the command registers.
PDOWN[1:0]:
Low power mode settings (Only specific functions are enabled.)
00: Normal operation (initial value)
01: Only the oscillator amplifier is enabled.
10: Only the oscillator amplifier and the output clock divider are enabled.
11: Reserved
PLLOPR:
PLL (VCO) operate/stop setting
0: Operate (initial value)
1: Stop
PLLCK[1:0]:
Clock frequency setting in the PLL locked state
00: 256fs (initial value)
01: 384fs
10: 512fs
11: (512/2)fs = 256fs
MCKHFO:
Frequency setting of CKOUT output clock
0: 1/1 output (initial value)
1: 1/2 output
• It is possible to maintain clock continuity when switching from the 512fs setting with PLLCK[1:0] = "10" to the
(512/2) fs setting with PLLCK[1:0] = "11", and switching vice versa without entering the PLL lock error state.
• For systems that must minimize power consumption such as portable equipment, we recommend the PLLCK[1:0] =
"00" (256fs) setting. For systems that require improved performance such as AV amplifiers, we recommend the
PLLCK[1:0] = "10" (512fs) or PLLCK[1:0] = "11" (512/2fs) setting.
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