LC89052T Datasheet, PDF (13/42 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89052T
8.3.3 Output clocks (CKOUT, BCK, LRCK)
• The clock source for the clocks output from CKOUT, BCK, and LRCK can be selected from two master clocks, the
PLL circuit and the XIN pin.
• Normally, when the PLL circuit is locked, the master clock is switched to the PLL source, and when the PLL circuit is
unlocked, the master clock automatically switches to the XIN source. To switch the clock source forcibly, set with
OCKSEL. Clock continuity is maintained when the clock source is selected by the locked/unlocked state of the PLL
circuit or OCKSEL.
• Clock switching depends on the PLL circuit locked/unlocked state at the time of the register setup. If the PLL source
is selected with OCKSEL when the PLL circuit is unlocked, the clock is automatically switched after the PLL circuit
is locked.
• When VCO operation is stopped with PLLOPR, XIN becomes the clock source. However, clock continuity cannot be
maintained if the operation is stopped with PLLOPR while the PLL circuit is locked. When a low-power mode is set,
continuity cannot be maintained if the mode is switched from the locked PLL.
OCKSEL
PLL state
Clock source
Table 8.4 Register Settings, PLL States, and the Clock Source
0
1
Locked
Unlocked
Locked
PLL
XIN
XIN
Unlocked
XIN
• Either the PLL clock or the XIN clock is output from the CKOUT pin. The divided clock of CKOUT is output from
the BCK pin and LRCK pin.
• The PLL lock time frequency is set with PLLCK[1:0]. However, it is possible to maintain clock continuity without
losing the PLL locked state when switching, in the PLL locked state, from the 512fs setting mode with PLLCK[1:0] =
"10" to the (512/2)fs setting with the PLLCK[1:0] = "11", as well as when switching in the reverse direction.
• If you use the following procedure to switch between 512fs and (512/2)fs, the BCK and LRCK output clock
continuity can be maintained, and the CKOUT output clock frequency can be held within a narrow band. Other
PLLCK[1:0] switching would result in a lock error.
512fs set
Data input
PLLCK0=0
PLLCK1=1
No _LOCK
detection
Yes
fs
calculation
fs=96kHz
fs=48kHz
CKOUT output
24.576MHz
(512/2)fs set
PLLCK0=1
PLLCK1=1
Figure 8.4 Flowchart for CKOUT Output Clock Narrow Band Operation
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