LC89052T Datasheet, PDF (26/42 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89052T
8.7.3 Output of clock switch transition sig_{__}n_{__}a_{___}l_{___}
• This section describes the operation when UGPI is selected as an output pin during the clock switching transitional
period.
• A clock switching transitional period signal is a signal that reports a clock switching condition to external circuits due
to a change in the PLL locked/unlocked state. This signal allows the application to grasp the PLL lock state
transitions and the timing of change in the clock_{__}s_{_}i_{__}g_{__}n_{__}a_{_}ls. This setup is selected with GPISEL.
• After setting GPISEL, high level is output from UGPI. Low pulse is output when the output clock changes due to the
change in the PLL circuit _{_}l_{_}o_{__}c_{__}k_{__}e_{_}d_{_} /unlocked state.
• In the lock in process, the UGPI low pulse rises with the word clock generated by the XIN clock after input data is
detected and PLL is locke_{_}d_{__}._{__}A_{___}f_{_}t_{_}er a certain period, it rises with the same timing as ERROR.
• In the unlock process, the UGPI low pulse falls at the same timing as ERROR, which is the PLL lock detecting signal
and it rises after the word clocks generated from the XIN clock are counted for a certain period.
RXIN
PLL lock state
XTAL clock
VCO clock
UGPI
ERROR
CKOUT
Unlocked
Digital data
Locked
15 ms to 50 ms _{With the same timing}
After PLL lock
as ERROR
(a) : During the lock-in process
RXIN
PLL lock state
XTAL clock
VCO clock
UGPI
ERROR
CKOUT
Digital data
Locked
Unlocked
64/fs (sec)
With the same timing as ERROR
(b) : During the unlock process
Figure 8.14 Clock Switching Timing
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