LC89052T Datasheet, PDF (10/42 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89052T
• The table below summaries the low-power modes.
Mode
(1)
(2)
(3)
(4)
(5)
(6)
(7)
___
PD
Low
High
AMPOPR
×
0
0
0
0
1
1
Table8.1 Low-power Modes
PLLOPR
PDOWN1
PDOWN0
×
×
×
0
0
0
1
0
0
×
0
1
×
1
0
0
0
0
1
×
×
Function
Reset (stand-by)
Normal operation
VCO stopped.
All circuits except the oscillator amplifier
stopped.
All circuits except the oscillator amplifier and
divider circuit stopped.
Oscillator amplifier stopped.
All circuits stopped.
• The table below lists the output pin states in the above modes.
Table 8.2 Output Pin States in Modes (1) to (7)
Output pin
______
AUDIO
_____
UGPI
Mode (1)
Low
High
Mode (2)
Output
Output
Mode (3)
Low
Output
Mode (4)
Low
Output
Mode (5)
Low
Output
Mode (6)
Output
Output
Mode (7)
Low
Output
CKOUT
Low
Output
Output
Output
Output
Output
Low
BCK
Low
Output
Output
Low
Output
Output
L or H
LRCK
Low
Output
Output
Low
Output
Output
L or H
DATAO
Low
Output
Output
Low
Output
Output
Low
XOUT
High
Output
Output
Output
Output
High
High
ERROR
High
Output
High
High
High
Output
High
E/INT
Low
Output
Low
Low
Low
Output
Low
1) In modes (3), (4), and (5), the clock supplied from the XIN pin is used as the source.
2) Mode (3) applies to the state where an external clock other than CKOUT is supplied to XIN. If XIN pin and CKOUT
pin are connected, no clock signals are output in this mode.
3) Mode (6) applies when the PLL circuit is locked.
When the PLL circuit is unlocked, all circuits are stopped since no clock signal is supplied from XIN pin.
4) In mode (7), the states immediatly before the setup is retained.
No.7457-10/42