K1S321615M Datasheet, PDF (8/12 Pages) Samsung semiconductor – 2Mx16 bit Uni-Transistor Random Access Memory

K1S321615M
TIMING WAVEFORM OF WRITE CYCLE(3)(UB, LB Controlled, ZZ=VIH)
Address
CS
UB, LB
WE
Data in
tAS(3)
tWC
tCW(2)
tAW
tBW
tWP(1)
tWR(4)
tDW
tDH
Data Valid
Data out
High-Z
High-Z
UtRAM
(WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition
when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
TIMING WAVEFORM OF DEEP POWER DOWN MODE
ZZ
Normal Operation
MODE
1µs
Suspend
Read Operation Twice or Stay High during 300µs
200µs
Wake up
Normal Operation
Deep Power Down Mode
CS
-8-
Revision 3.0
May 2001