K1S321615M Datasheet, PDF (11/12 Pages) Samsung semiconductor – 2Mx16 bit Uni-Transistor Random Access Memory

TECHNICAL
NOTE
TNAL0001
UtRAM USAGE AND TIMING
UtRAM USAGE AND TIMING
INTRODUCTION
UtRAM is based on single-transistor DRAM cells. As with any
other DRAM, the data in these cells must be periodically
refreshed to prevent data loss. What makes the UtRAM unique
is that it offers a true SRAM style interface that hides all refresh
operations from the memory controller.
START WITH A DRAM TECHNOLOGY
The key to the UtRAM is its high speed and low power. This
speed comes from the use of many small blocks, often just
32Kbits each, to create UtRAM arrays. The small blocks have
short word lines with little capacitance, eliminating a major
source of operating current in conventional DRAM blocks.
Each independent macro-cell on a UtRAM device consists of a
number of these blocks. Each chip has one or more macro.
The address decoding logic is also fast. UtRAM perform a
complete read operation in every tRC, but UtRAM needs power
up sequence like a DRAM.
Power Up Sequence and Diagram
1. Apply power.
2. Maintain stable power for a minium 200µs with CS=high.
3. Issue read operation at least 2 times.
Power On
CS=VIH
CS=VIL, UB or/and LB=VIL
ZZ=VIH
Initial State
(Wait 200µs)
Active
Read Operation(2 times)
Figure 1.
CS
Over 4us
DESIGN ACHIEVES SRAM SPECIFIC
OPERATIONS
The UtRAM design works just like an SRAM, with no wait
states or other overhead for precharging or refreshing its inter-
nal DRAM cells. SAMSUNG Electronics(SAMSUNG) hides
these operations with advanced design. Precharging takes
place during every access, overlapped with the end of the cycle
and the decoding portion of the next cycle.
Hiding refresh is more difficult, Every row in every block must
be refreshed at least once during the refresh interval to prevent
data loss. SAMSUNG provides a internal refresh controller for
devices. When all accesses during a refresh interval are
directed to one macro-cell, as can happen in signal processing
applications, a more sophisticated approach is required to hide
refresh. The pseudo SRAM, sometimes used on these applica-
tions, which is required a memory controller that can hold off
accesses when a refresh operation is needed. SAMSUNG
unique qualitative advantage over these parts(in addition to
quantitative improvements in access speed and power con-
sumption) is that the UtRAM never needs to hold off accesses,
and indeed it has no hold off signal. The circuitry that gives
SAMSUNG this advantage is fairly simple but has not previ-
ously been disclosed.
AVOID TIMING
Following figures are show you a abonormal timing which is
not supported on UtRAM and their solution.
At read operation, if your system have a timing which sustain
invalid states over 4us at read mode like Figure 1. There are
some guide line for proper operation of UtRAM.
When your system have multiple invalid address signal shorter
than tRC on the timing which showed in Figure 1, UtRAM need
a normal read timing during that cycle(Figure 2) or toggle the
CS to h’ igh’about t’RC(’Figure 3).
WE
Less than tRC
Address
Figure 2.
CS
Over 4us
Put on read operation every 4us
WE
tRC
Address
SRAM/NVM PLANNING
YOON-000831
SAMSUNG Electronics CO., LTD. reserves the right to change products or specifications without notice.
©2000 SAMSUNG Electronics CO., LTD.
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