K4R761869A-F Datasheet, PDF (7/20 Pages) Samsung semiconductor – 576Mbit RDRAM (A-die) 1M x 18bit x 32s banks Direct RDRAMTM

K4R761869A
Direct RDRAM^™
General Description
Figure 2 is a block diagram of the 576Mbit RDRAM device.
It consists of two major blocks: a “core” block built from
banks and sense amps similar to those found in other types
of DRAM, and a Direct Rambus^TM interface block which
permits an external controller to access this core at up to
2.4GB/s.
Control Registers: The CMD, SCK, SIO0 and SIO1
pins appear in the upper center of Figure 2. They are used to
write and read a block of control registers. These registers
supply the RDRAM configuration information to a
controller and they select the operating modes of the device.
The REFR value is used for tracking the last refreshed row.
Most importantly, the five bit DEVID specifies the device
address of the RDRAM device on the Channel.
Clocking: The CTM and CTMN pins (Clock-To-Master)
generate TCLK (Transmit Clock), the internal clock used to
transmit read data. The CFM and CFMN pins (Clock-From-
Master) generate RCLK (Receive Clock), the internal clock
signal used to receive write data and to receive the ROW and
COL pins.
DQA,DQB Pins: These 18 pins carry read (Q) and write
(D) data across the Channel. They are multiplexed/de-multi-
plexed from/to two 72-bit data paths (running at one-eighth
the data frequency) inside the RDRAM device.
Banks: The 64Mbyte core of the RDRAM device is
divided into thirty two 2Mbyte banks, each organized as
1024 rows, with each row containing 128 dualocts, and each
dualoct containing 18 bytes. A dualoct is the smallest unit of
data that can be addressed.
Sense Amps: The RDRAM device contains 34 sense
amps. Each sense amp consists of 1kbyte of fast storage (512
bytes for DQA and 512 bytes for DQB) and can hold one-
half of one row of one bank of the RDRAM device. The
sense amp may hold any of the 1024 half-rows of an associ-
ated bank. However, each sense amp is shared between two
adjacent banks of the RDRAM device (except for sense
amps 0, 15, 16, and 31). This introduces the restriction that
adjacent banks may not be simultaneously accessed.
RQ Pins: These pins carry control and address informa-
tion. They are broken into two groups. RQ7..RQ5 are also
called ROW2..ROW0, and are used primarily for controlling
row accesses. RQ4..RQ0 are also called COL4..COL0, and
are used primarily for controlling column accesses.
ROW Pins: The principle use of these three pins is to
manage the transfer of data between the banks and the sense
amps of the RDRAM device. These pins are de-multiplexed
into a 24-bit ROWA (row-activate) or ROWR (row-opera-
tion) packet.
COL Pins: The principle use of these five pins is to
manage the transfer of data between the DQA/DQB pins and
the sense amps of the RDRAM device. These pins are de-
multiplexed into a 23-bit COLC (column-operation) packet
and either a 17-bit COLM (mask) packet or a 17-bit COLX
(extended-operation) packet.
ACT Command: An ACT (activate) command from an
ROWA packet causes one of the 1024 rows of the selected
bank to be loaded to its associated sense amps (two 512
bytes sense amps for DQA and two for DQB).
PRER Command: A PRER (precharge) command from
an ROWR packet causes the selected bank to release its two
associated sense amps, permitting a different row in that
bank to be activated, or permitting adjacent banks to be acti-
vated.
RD Command: The RD (read) command causes one of
the 128 dualocts of one of the sense amps to be transmitted
on the DQA/DQB pins of the Channel.
WR Command: The WR (write) command causes a
dualoct received from the DQA/DQB data pins of the
Channel to be loaded into the write buffer. There is also
space in the write buffer for the BC bank address and C
column address information. The data in the write buffer is
automatically retired (written with optional bytemask) to one
of the 128 dualocts of one of the sense amps during a subse-
quent COP command. A retire can take place during a RD,
WR, or NOCOP to another device, or during a WR or
NOCOP to the same device. The write buffer will not retire
during a RD to the same device. The write buffer reduces the
delay needed for the internal DQA/DQB data path turn-
around.
PREC Precharge: The PREC, RDA and WRA
commands are similar to NOCOP, RD and WR, except that a
precharge operation is performed at the end of the column
operation. These commands provide a second mechanism
for performing precharge.
PREX Precharge: After a RD command, or after a WR
command with no byte masking (M=0), a COLX packet may
be used to specify an extended operation (XOP). The most
important XOP command is PREX. This command provides
a third mechanism for performing precharge.
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Version 1.41 Jan. 2004