K4R761869A-F Datasheet, PDF (5/20 Pages) Samsung semiconductor – 576Mbit RDRAM (A-die) 1M x 18bit x 32s banks Direct RDRAMTM

K4R761869A
Direct RDRAM^™
Signal
SIO1,SIO0
I/O Type
I/O CMOS^a
CMD
I CMOS^a
SCK
V_DD
V_DDa
V_CMOS
GND
GNDa
DQA8..DQA0
I CMOS^a
I/O RSL^b
CFM
I RSL^b
CFMN
V_REF
CTMN
I RSL^b
I RSL^b
CTM
I RSL^b
RQ7..RQ5 or
ROW2..ROW0
RQ4..RQ0 or
COL4..COL0
I RSL^b
I RSL^b
DQB8..
DQB0
I/O RSL^b
Total pin count per package
Table 2: Pin Description
# Pins
center
Description
2
Serial input/output. Pins for reading from and writing to the control regis-
ters using a serial access protocol. Also used for power management.
Command input. Pins used in conjunction with SIO0 and SIO1 for reading
1
from and writing to the control registers. Also used for power manage-
ment.
1
Serial clock input. Clock source used for reading from and writing to the
control registers
24
Supply voltage for the RDRAM core and interface logic.
1
Supply voltage for the RDRAM analog circuitry.
2
Supply voltage for CMOS input/output pins.
28
Ground reference for RDRAM core and interface.
2
Ground reference for RDRAM analog circuitry.
Data byte A. Nine pins which carry a byte of read or write data between
9
the Channel and the RDRAM device. DQA8 is not used (no connection)
by RDRAM device with a x16 organization.
1
Clock from master. Interface clock used for receiving RSL signals from
the Channel. Positive polarity.
1
Clock from master. Interface clock used for receiving RSL signals from
the Channel. Negative polarity
1
Logic threshold reference voltage for RSL signals
1
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Negative polarity.
1
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Positive polarity.
3
Row access control. Three pins containing control and address informa-
tion for row accesses.
5
Column access control. Five pins containing control and address informa-
tion for column accesses.
Data byte B. Nine pins which carry a byte of read or write data between
9
the Channel and the RDRAM device. DQB8 is not used (no connection)
by RDRAM device with a x16 organization.
92
a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
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Version 1.41 Jan. 2004