K4R761869A-F Datasheet, PDF (12/20 Pages) Samsung semiconductor – 576Mbit RDRAM (A-die) 1M x 18bit x 32s banks Direct RDRAMTM

K4R761869A
Direct RDRAM^™
Electrical Conditions
Table 9: Electrical Conditions
Symbol
T_J
V_DD, V_DDA
V_DD,N, V_DDA,N
v_DD,N, v_DDA,N
V_CMOSa
V_REF
V_DIL
V_DIH
R_DA
V_CM
V_CIS,CTM
V_CIS,CFM
V_IL,CMOS
V_IH,CMOS
Parameter and Conditions
Junction temperature under bias
Supply voltage
Supply voltage droop (DC) during NAP interval (t_NLIMIT)
Supply voltage ripple (AC) during NAP interval (t_NLIMIT)
Supply voltage for CMOS pins (2.5V controllers)
Supply voltage for CMOS pins (1.8V controllers)
Reference voltage
RSL data input - low voltage @ t_CYCLE=1.667ns
RSL data input - low voltage @ t_CYCLE=1.875ns
RSL data input - low voltage @ t_CYCLE=2.50ns
RSL data input - high voltage^b @ t_CYCLE=1.667ns
RSL data input - high voltage^b @ t_CYCLE=1.875ns
RSL data input - high voltage^b @ t_CYCLE=2.50ns
RSL data asymmetry : R_DA = (V_DIH - V_REF) / (V_REF - V_DIL)
RSL clock input - common mode V_CM = (V_CIH+V_CIL)/2
RSL clock input swing: V_CIS = V_CIH - V_CIL (CTM,CTMN pins).
RSL clock input swing: V_CIS = V_CIH - V_CIL (CFM,CFMN pins).
CMOS input low voltage
CMOS input high voltage
Min
-
2.50 - 0.13
-
-2.0
V_DD
1.80 - 0.1
1.40 - 0.2
V_REF - 0.5
V_REF - 0.5
V_REF - 0.5
V_REF + 0.15
V_REF + 0.15
V_REF + 0.2
0.67
1.3
0.35
0.225
- 0.3^c
V_CMOS/2 + 0.25
Max
100
2.50 + 0.13
2.0
2.0
V_DD
1.80 + 0.2
1.40 + 0.2
V_REF - 0.15
V_REF - 0.15
V_REF - 0.2
V_REF + 0.5
V_REF + 0.5
V_REF + 0.5
1.00
1.8
1.00
1.00
V_CMOS/2 - 0.25
V_CMOS+0.3^d
a. V_CMOS must remain on as long as V_DD is applied and cannot be turned off.
b. V_DIH is typically equal to V_TERM (1.8V±0.1V) under DC conditions in a system.
c. Voltage undershoot is limited to -0.7V for a duration of less than 5ns.
d. Voltage overshoot is limited toV_CMOS +0.7V for a duration of less than 5ns
Unit
°C
V
%
%
V
V
V
V
V
-
V
V
V
V
V
Page 10
Version 1.41 Jan. 2004