K4R761869A-F Datasheet, PDF (15/20 Pages) Samsung semiconductor – 576Mbit RDRAM (A-die) 1M x 18bit x 32s banks Direct RDRAMTM

K4R761869A
Direct RDRAM^™
Table 11: Timing Conditions
Symbol
t_S2
t_H2
t_S3
t_H3
t_S4
t_H4
t_NPQ
t_READTOCC
t_CCSAMTOREAD
t_CE
t_CD
t_FRM
t_NLIMIT
t_REF
t_BURST
t_CCTRL
t_TEMP
t_TCEN
t_TCAL
t_TCQUIET
t_PAUSE
Parameter
SIO0 setup time to SCK falling edge
SIO0 hold time to SCK falling edge
PDEV setup time on DQA5..0 to SCK rising edge.
PDEV hold time on DQA5..0 to SCK rising edge.
ROW2..0, COL4..0 setup time for quiet window
ROW2..0, COL4..0 hold time for quiet window^f
Quiet on ROW/COL bits during NAP/PDN entry
Offset between read data and CC packets (same device)
Offset between CC packet and read data (same device)
CTM/CFM stable before NAP/PDN exit
CTM/CFM stable after NAP/PDN entry
ROW packet to COL packet ATTN framing delay
Maximum time in NAP mode
Refresh interval
Interval after PDN or NAP (with self-refresh) exit in which all banks
of the RDRAM device must be refreshed at least once.
Current control interval
Temperature control interval
TCE command to TCAL command
TCAL command to quiet window
Quiet window (no read data)
RDRAM device delay (no RSL operations allowed)
Min
40
40
0
5.5
-1
5
4
12
8
2
100
7
34 t_CYCLE
150
2
140
Max
-
-
-
-
-
-
-
-
-
-
-
-
10.0
32
200
100ms
100
-
2
-
200.0
Unit
ns
ns
ns
ns
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
ms
ms
Figure(s)
Figure 59
Figure 59
Figure 50
Figure 60
Figure 50
Figure 50
Figure 49
Figure 54
Figure 54
Figure 50
Figure 49
Figure 48
Figure 47
Figure 52
ms
Figure 53
ms/t_CYCLE
ms
t_CYCLE
t_CYCLE
t_CYCLE
ms
Figure 54
Figure 55
Figure 55
Figure 55
Figure 55
page 38
a. MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is effectively 0.0 to 0.0.
b. t_S,MIN and t_H,MIN for other t_CYCLE values can be interpolated between or extrapolated from the timings at the 2 specified t _CYCLE values.
c. This parameter also applies to a-1200 part when operated with t_CYCLE = 1.875ns
d. This parameter also applies to a-1200 or -1066 part when operated with t_CYCLE = 2.50ns
e. With V_IL,CMOS=0.5V_CMOS-0.4V and V_IH,CMOS=0.5V_CMOS+0.4V
f. Effective hold becomes t_H4’=t_H4+[PDNXA•64•t_SCYCLE+t_PDNXB,MAX]-[PDNX•256•t_SCYCLE] if [PDNX•256•t_SCYCLE] < [PDNXA•64•t_SCYCLE+t_PD-
NXB,MAX^{]. See Figure 50}
Page 13
Version 1.41 Jan. 2004