DS_K9K1208U0A Datasheet, PDF (7/27 Pages) Samsung semiconductor – 64M x 8 Bit NAND Flash Memory

K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
VALID BLOCK
Parameter
Valid Block Number
Symbol
NVB
Min
4,026
Typ.
-
Max
4,096
Unit
Blocks
NOTE :
1. The K9K1208U0A may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid
blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try
to access these invalid blocks for program and erase. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block
AC TEST CONDITION
(K9K1208U0A-YCB0 :TA=0 to 70°C, K9K1208U0A-YIB0:TA=-40 to 85°C, VCC=2.7V~3.6V unless otherwise)
Parameter
Value
Input Pulse Levels
0.4V to 2.4V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load (3.0V +/-10%)
1 TTL GATE and CL=50pF
Output Load (3.3V +/-10%)
1 TTL GATE and CL=100pF
CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
Test Condition
Min
CI/O
VIL=0V
-
CIN
VIN=0V
-
Max
30
30
Unit
pF
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
ALE
CE
WE
RE
WP
Mode
H
L
L
L
H
L
H
X
Command Input
Read Mode
H
X
Address Input(4clock)
H
L
L
L
H
L
H
H
Command Input
Write Mode
H
H
Address Input(4clock)
L
L
L
H
H
Data Input
L
L
L
H
X
sequential Read & Data Output
L
L
L
H
H
X
During Read(Busy)
X
X
X
X
X
H
During Program(Busy)
X
X
X
X
X
H
During Erase(Busy)
X
X⁽¹⁾
X
X
X
L
Write Protect
X
X
H
X
X
0V/VCC⁽²⁾ Stand-by
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
Program/Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Program Time
tPROG
-
200
500
Number of Partial Program Cycles
in the Same Page
Main Array
Spare Array
Nop
-
-
-
-
2
3
Block Erase Time
tBERS
-
2
3
Unit
µs
cycles
cycles
ms
7