DS_K9K1208U0A Datasheet, PDF (13/27 Pages) Samsung semiconductor – 64M x 8 Bit NAND Flash Memory

K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-
ing would provide significant savings in power consumption.
Figure 3. Program Operation with CE don’t-care.
CLE
CE
CE don’t-care
WE
ALE
I/O0~7
CE
80h Start Add.(4Cycle)
(Min. 10ns)
tCS
tCH
Data Input
CE
Data Input
10h
(Max. 45ns)
tCEA
tWP
WE
RE
I/O0~7
tREA
out
Timing requirements : If CE is is exerted high during data-loading, Timing requirements : If CE is exerted high during sequential
tCS must be minimum 10ns and tWC must be increased accordingly. data-reading, the falling edge of CE to valid data(tCEA) must
be kept greater than 45ns.
Figure 4. Read Operation with CE don’t-care.
CLE
CE
RE
ALE
R/B
Must be held
low during tR.
tR
CE don’t-care
WE
I/O0~7
00h
Start Add.(4Cycle)
Data Output(sequential)
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