DS_K9K1208U0A Datasheet, PDF (24/27 Pages) Samsung semiconductor – 64M x 8 Bit NAND Flash Memory

K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
Table2. Read Staus Register Definition
I/O #
I/O 0
Status
Program / Erase
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Reserved for Future
Use
Device Operation
Write Protect
Definition
"0" : Successful Program / Erase
"1" : Error in Program / Erase
"0"
"0"
"0"
"0"
"0"
"0" : Busy
"1" : Ready
"0" : Protected
"1" : Not Protected
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Two read cycles sequentially output the manufacture code(ECH), and the device code (76H) respectively. The command regis-
ter remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence.
Figure 9. Read ID Operation
CLE
CE
WE
ALE
RE
I/O0~7
tCR
tAR1
tREADID
90h
00h
ECh
76h
Address. 1cycle
Maker code
Device code
24