DS_K9K1208U0A Datasheet, PDF (4/27 Pages) Samsung semiconductor – 64M x 8 Bit NAND Flash Memory

K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
PRODUCT INTRODUCTION
The K9K1208U0A is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen col-
umns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating
data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of
16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the
32 pages formed by two NAND structures, totaling 8,448 NAND structures of 16 cells. The array organization is shown in Figure 2.
The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The mem-
ory array consists of 4,096 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
K9K1208U0A.
The K9K1208U0A has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block
address loading. The 64M byte physical space requires 26 addresses, thereby requiring four cycles for byte-level addressing: col-
umn address, low row address and high row address, in that order. Page Read and Page Program need the same four address
cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device
operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the
K9K1208U0A.
Table 1. COMMAND SETS
Function
1st. Cycle
2nd. Cycle
Acceptable Command during Busy
Read 1
00h/01h⁽¹⁾
-
Read 2
50h
-
Read ID
90h
-
Reset
FFh
-
O
Page Program
80h
10h
Block Erase
60h
D0h
Read Status
70h
-
O
NOTE : 1. The 00h command defines starting address of the 1st half of registers.
The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half
register(00h) on the next cycle.
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