DS_S5T8702 Datasheet, PDF (60/62 Pages) Samsung semiconductor – FEEX ALPHANUMERIC DECODER II

S5T8702
FEEX^TM ALPHANUMERIC DECODER II
Reset Timing
The following diagram and table describe the timing specifications of the S5T8702 when it is reset.
RESET
READY
tRL
tRLRH
tRHRL
Figure 17: Reset Timing
Table 38: Reset Timing (V_DD = 1.8V to 3.6V, Ta = -25°C to 85°C)
Characteristic
Conditions
Symbol
Min
Typ
RESET Pulse Width
t_RL
200
RESET Low to READY High
t_RLRH
-
RESET High to READY Low ^{Requires stable clock}
t_RHRL
1
Max Unit
-
ns
200
ns
sec
60