DS_S5T8702 Datasheet, PDF (59/62 Pages) Samsung semiconductor – FEEX ALPHANUMERIC DECODER II

FEEX^TM ALPHANUMERIC DECODER II
S5T8702
Start-up Timing
The following diagram and table describe the timing specifications of the S5T8702 when power is applied.
VDD
Oscillator
tSTART
RESET
READY
tRESET
tOWRL
tRHRL
Figure 16: Start-up Timing
Table 37: Start-up Timing (V_DD = 1.8V to 3.6V, Ta = -25°C to +85°C)
Characteristic
Conditions
Symbol
Min
Typ
Oscillator Start-up Time
RESET Hold Time
t_START
t_RESET
200
RESET High to READY Low ^a
t_RHRL
1
Oscillator Warmed up to READY
CL=50pf
t_OWRL
1
Low ^a
Max Unit
5
sec
ns
sec
sec
a.
Note that from power-up, the oscillator start-up time can impact the availability and period of
clock strobes. This can affect the actual RESET high to READY low timing.
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