DS_S5T8702 Datasheet, PDF (25/62 Pages) Samsung semiconductor – FEEX ALPHANUMERIC DECODER II

FEEX^TM ALPHANUMERIC DECODER II
S5T8702
3200SPS SYNC SETTING PACKETS
Byte 3
Byte 2
Byte 1
Byte 0
Table 13: 3200sps Sync Setting Packet Bit Assignments
Bit 7
0
0
CLS₇
0
Bit 6
0
0
CLS₆
ST₆
Bit 5
0
0
CLS₅
ST₅
Bit 4
1
0
CLS₄
ST₄
Bit 3
0
LBC
CLS₃
ST₃
Bit 2
1
0
CLS₂
ST₂
Bit 1
1
0
CLS₁
ST₁
Bit 0
0
0
CLS₀
ST₀
LBC:
CLS:
ST:
Low Battery Check. If this bit is set, the S5T8702 will check the status of the LOBAT port just
before leaving this receiver state. (value after reset=0)
Control Line Setting. This is the value to be output on the receiver control lines (SO - S7) for this
receiver state. (value after reset=0)
Step Time. This is the time the S5T8702 is to wait before expecting good signals on the EXTS1 and
EXTS0 signals after warming up. The setting is in steps of 625us. Valid values are 625us (ST=01)
to 79.375ms (ST=7F in hexadecimal). (value after reset=625us)
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