DS_S5T8702 Datasheet, PDF (3/62 Pages) Samsung semiconductor – FEEX ALPHANUMERIC DECODER II

FEEX^TM ALPHANUMERIC DECODER II
SYSTEM BLOCK DIAGRAM
S5T8702
Receiver
Synthesizer
Programming Control
Receiver
Control
S0/IFIN
S5T8702
Host
Microprocessor
User
Interface
38.4 or 40 kHz Clock
15pF
Low Battery ^LOBAT
Detector
15pF
Figure 1 : Example Block Diagram Using Internal Demodulator
When configured to use the internal demodulator, the S5T8702 connects to a receiver capable of generating a
limited (i.e. 1-bit digitized) 455kHz or 140kHz IF signal. In this mode, the S5T8702 has 7 receiver control lines
used for warming up and shutting down a receiver in stages. The S5T8702 has the ability to detect a low battery
signal during the receiver control sequences. It interfaces to a host MCU through a standard SPI. It has a 1minute
timer that offers low power support for a time of day function on the host.
When using the internal demodulator, the oscillator frequency (or external clock) must be 160kHz. The CLKOUT
signal can be programmed to be either a 38.4kHz signal created by fractionally dividing the oscillator clock, or a
40kHz signal creating by dividing the oscillator clock by 4.
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