DS_S5T8702 Datasheet, PDF (15/62 Pages) Samsung semiconductor – FEEX ALPHANUMERIC DECODER II

FEEX^TM ALPHANUMERIC DECODER II
S5T8702
CONFIGURATION PACKET
The Configuration Packet defines a number of different configuration options for the S5T8702. Proper operation
is not guaranteed if these settings are changed when decoding is enabled (i.e. the ON bit in the Control Packet is
set). The ID of the Configuration Packet is 1.
Byte 3
Byte 2
Byte 1
Byte 0
Bit 7
0
0
0
SME
Table 4: Configuration Packet Bit Assignments
Bit 6
0
DFC
0
MOT
Bit 5
0
0
0
COD
Bit 4
0
0
0
MTE
Bit 3
0
0
0
LBP
Bit 2
0
IDE
PCE
ICO
Bit 1
0
OFD₁
SP₁
0
Bit 0
1
OFD₀
SP₀
0
DFC:
Disable Fractional Clock. When this bit is set and IDE is set, the CLKOUT signal will generate a
40kHz signal (EXTAL divided by 4). When this bit is cleared and IDE is set, the CLKOUT signal will
generate 38.4kHz signal (EXTAL fractionally divided by 25/6 see diagram below). This bit has no
effect when IDE is cleared. (value after reset=0)
EXTAL
CLKOUT
w/DFC=1
CLKOUT
w/DFC=0
IDE:
Internal Demodulator Enable. When this bit is set, the internal demodulator is enabled and clock
frequency at EXTAL is expected to be 160kHz. When this bit is cleared, the internal demodulator is
disabled and the clock frequency at EXTAL is expected to be 76.8kHz. (value after reset=0)
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