DS_S5T8702 Datasheet, PDF (6/62 Pages) Samsung semiconductor – FEEX ALPHANUMERIC DECODER II

S5T8702
FEEX^TM ALPHANUMERIC DECODER II
PIN DESCRIPTION
PIN NAME
V_DD
V_SS
LOBAT
RESET
EXTS1
EXTS0
SS
SCK
MOSI
MISO
READY
CLKOUT
SYMCLK
EXTAL
XTAL
OSCPD
S1 - S7
S0 / IFIN
TEST2, TEST3
NC
PIN
3,13
7,29
10
24
11
12
27
28
30
31
26
32
14
6
5
2
22,21,20,1
9,18,16,15
23
4,8
1,9,17,25
TYPE
I
I
DESCRIPTION
Power
Power
Ground
Low battery detect input
Reset
Active low reset to the S5T8702.
External Symbol Input Signals
I
MSb of the symbol currently being decoded
I
LSb of the symbol currently being decoded
SPI Signals
I
Slave Select for SPI communications
I
Serial Clock for SPI communications
I
Data input for SPI communications
O
Three-state data output for SPI communications
O
Driven low when the IC is ready for an SPI packet
Clock Signals
O
38.4 kHz or 40kHz clock output(derived from oscillator)
O
Recovered symbol clock
I
76.8 kHz or 160kHz crystal input or external input
O
76.8 kHz or 160kHz clock output
I
Internal oscillator power down.
Connected to VSS when using internal oscillator.
Connected to VDD when using an external source.
Receiver Control Lines
O
Seven three-state receiver control output
O / I S0 : Receiver control output when using external
demodulator
IFIN : Limited IF input when using internal demodulator
Test pins
I
IC manufacturing test mode pin.
Normally connected to VSS.
O
IC manufacturing test mode on.
Normally connected to Vss. (Can be left unconnected.)
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