DS_S5T8702 Datasheet, PDF (41/62 Pages) Samsung semiconductor – FEEX ALPHANUMERIC DECODER II

FEEX^TM ALPHANUMERIC DECODER II
S5T8702
STATUS PACKET
The Status Packet contains various types of information that the host may require. The Status Packet will be sent
to the host whenever the S5T8702 is polled and has no other data to send. The S5T8702 can also prompt the
host to read the Status Packet due to events for which the S5T8702 was configured to send it (see "Configuration
Packet" on page 18 and "Control Packet" on page 20 for a detailed description of the bits). The S5T8702 will
prompt the host to read a Status Packet if the...
1. ... SMU bit in the Status Packet and the SME bit in the Configuration Packet are set.
2. ... MT bit in the Status Packet and the MTE bit in the Configuration Packet are set.
3. ... EOF bit in the Status Packet is set.
4. ... LBU bit in the Status Packet is set.
5. ... EA bit in the Status Packet is set.
6. ... BOE bit in the Status Packet is set.
The ID of the Status Packet is 127 (decimal).
Byte 3
Byte 2
Byte 1
Byte 0
Bit 7
0
FIV
SM
SMU
Table 28: Status Packet Bit Assignments
Bit 6
1
f₆
LB
LBU
Bit 5
1
f₅
x
x
Bit 4
1
f₄
x
MT
Bit 3
1
f₃
c₃
x
Bit 2
1
f₂
c₂
EOF
Bit 1
1
f₁
c₁
EA
Bit 0
1
f₀
C₀
BOE
FIV:
Frame Info Valid. Set when a valid frame info word has been received since becoming synchronous
to the system and the f and c fields contain valid values. If this bit is clear, no valid frame info
words have been received since the S5T8702 became synchronous to the system. This value will
change from 0 to 1 at the end of block 0 of the frame in which the 1st frame info word was properly
received. It will be cleared when the S5T8702 goes into asynchronous mode. This bit is initialized to
0 when the S5T8702 is reset and when the S5T8702 is turned off by clearing the ON bit in the
Control Packet.
f:
Current frame number. This value is updated every frame regardless of whether the S5T8702
needs to decode the frame. This value will change to its proper value for a frame at the end of
block 0 of the frame. The value of these bits is not guaranteed when FIV is 0.
SM:
Synchronous Mode. This bit is set when the S5T8702 is synchronous to the system. The S5T8702
will set this bit when the first synchronization words are received. It will clear this bit when the
S5T8702 has not received both synchronization words in any frame for 8, 16, or 32 minutes
(depending on the number of assigned frames and the system collapse). This bit is initialized to 0
when the S5T8702 is reset and when it is turned off by clearing the ON bit in the Control Packet
LB:
Low Battery. Set to the value last read from the LOBAT pin. The host controls when the LOBAT pin
is read via the Receiver Control Packets. This bit is initialized to 0 at reset. It is also initialized to the
inverse of the LBP bit in the Configuration Packet when the S5T8702 is turned on by setting the ON
bit in the Control Packet.
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