DS_S5T8702 Datasheet, PDF (58/62 Pages) Samsung semiconductor – FEEX ALPHANUMERIC DECODER II

S5T8702
FEEX^TM ALPHANUMERIC DECODER II
Table 36: SPI Timing (VDD = 1.8V to 3.6V Ta = -25°C to +85°C)
Characteristic
Operating Frequency
Cycle Time
Select Lead Time
De-select Lag Time
Select-to-Ready Time
Select-to-Ready Time
Ready High Time
Ready Lead Time
Not Ready Lag Time
MOSI Data Setup Time
MOSI Data Hold Time
MISO Access Time
MISO Disable Time
MISO Data Valid Time
MISO Data Hold Time
SS High Time
SCK High Time
SCK Low Time
SCK Rise Time
SCK Fall Time
Conditions
previous packet did not program an address
word ^a
CL=50pf
previous packet programmed an address
worda
CL=50pf
CL=50pf
CL=50pf
CL=50pf
20% to 70% V_DD
20% to 70% V_DD
Symbol
f_OP
t_CYC
t_LEAD1
t_LAG1
t_RDY
Min
0
1000
200
200
t_RDY
t_RH
50
t_LEAD2
200
t_LAG2
t_SU
200
t_HI
200
t_AC
0
t_DIS
t_V
t_HO
0
t_SSH
200
t_SCKH
300
t_SCKL
300
t_R
t_F
Max
1
80
420
200
200
300
200
1
1
Unit
MHz
ns
ns
ns
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
a.
When the host re-programs an address word with a Host-to-FLEX decoder packet ID >
127(decimal), there may be an added delay before the S5T8702 is ready for another packet.
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