K4H280438B-TCA0 Datasheet, PDF (52/53 Pages) Samsung semiconductor – 128Mb DDR SDRAM

128Mb DDR SDRAM
QFC timing on Write operation
QFC on writes is enabled as soon as possible after the clock edge of write command and disabled as soon
as possible after the last DQS-in low going edge.
BL = 2
0
1
2
3
4
5
6
7
8
CK
CK
Command
DQS@tDQSSmax
Write
DQS’ @tDQSSmax
QFC
Hi-Z _tQCSW
Dout 0 Dout 1
*2_{tQCHW max.}
*1_{tQCHW min.}
Figure 27. : QFC timing on write operation with tDQSSmax
CK
0
1
2
3
4
5
6
7
CK
Command
DQS@tDQSSmin
Write
DQS’ @tDQSSmin
QFC
Dout 0 Dout 1
Hi-Z _tQCSW
*1_{tQCHW min.} ^*2tQCHW max.
BL = 2
8
Figure 28. : QFC timing on write operation with tDQSSmin
1. The value of tQCSW min. is 1.25ns from the last low going data strobe edge to QFC tri-state.
2. The value of tQCSW max. is 0.5tcK from the first high going clock edge after the last low going data strobe
edge to QFC tri-state.
- 52 -
REV. 1.0 November. 2. 2000