K4H280438B-TCA0 Datasheet, PDF (28/53 Pages) Samsung semiconductor – 128Mb DDR SDRAM

128Mb DDR SDRAM
6. When terminating a burst Read command, the BST command must be issued L_BST (“BST Latency”) clock
cycles before the clock edge at which the output buffers are tristated, where L_BST equals the CAS latency
for read operations. This is shown in previous page Figure with examples for CAS latency (CL) of 1.5, 2,
2.5, 3 and 3.5 (only selected CAS latencies are required by the DDR SDRAM standards, the others are
optional).
7. When the burst terminates, the DQ and DQS pins are tristated.
The BST command is not byte controllable and applies to all bits in the DQ data word and the(all) DQS pin(s).
3.3.10 DM masking
The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle, not read
cycle. When the data mask is activated (DM high) during write operation, DDR SDRAM does not accept the
corresponding data.(DM to data-mask latency is zero).
DM must be issued at the rising or falling edge of data strobe.
< Burst Length=8 >
0
1
2
3
4
5
CK
CK
Command
DQS
WRITE
NOP
tDQSS
NOP
NOP
NOP
NOP
DQ ′s
Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din7
DM
6
NOP
7
NOP
8
NOP
masked by DM=H
Figure 18. DM masking timing
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REV. 1.0 November. 2. 2000