K4H280438B-TCA0 Datasheet, PDF (44/53 Pages) Samsung semiconductor – 128Mb DDR SDRAM

128Mb DDR SDRAM
8.2 AC Timming Parameters & Specifications
Parameter
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. address to Col. address delay
Clock cycle time
CL=2.0
CL=2.5
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
Data out high impedence time from CK/CK
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS-in high level width
DQS-in low level width
DQS-in cycle time
Address and Control Input setup time
Address and Control Input hold time
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
DQ & DM input pulse width
Power down exit time
Exit self refresh to write command
Symbol
tRC
tRFC
K4H281638B
-TCA2 (DDR266A)
Min
Max
65
75
K4H281638B
-TCB0 (DDR266B)
Min
Max
65
75
tRAS
tRCD
tRP
45
120K
45
120K
20
20
20
20
tRRD
15
15
tWR
2
2
tCDLR
tCCD
tCK
tCH
1
1
7.5
0.45
15
15
0.55
1
1
10
15
7.5
15
0.45
0.55
tCL
tDQSCK
tAC
tDQSQ
tRPRE
0.45
-0.75
-0.75
-
0.9
0.55
+0.75
+0.75
+0.5
1.1
0.45
-0.75
-0.75
-
0.9
0.55
+0.75
+0.75
+0.5
1.1
tRPST
tHZQ
0.4
-0.75
0.6
+0.75
0.4
-0.75
0.6
+0.75
tDQSS
0.75
tWPRES
0
tWPREH 0.25
1.25
0.75
1.25
0
0.25
tDQSH
0.4
0.6
0.4
0.6
tDQSL
0.4
0.6
0.4
0.6
tDSC
0.9
1.1
0.9
1.1
tIS
0.9
0.9
tIH
0.9
0.9
tMRD
15
15
tDS
0.5
0.5
tDH
0.5
0.5
tDIPW
1.75
tPDEX
10
tXSW
95
1.75
10
K4H281638B
-TCA0 (DDR200)
Min
Max
70
80
48
120K
20
20
15
2
1
1
10
15
15
0.45
0.55
0.45
0.55
-0.8
+0.8
-0.8
+0.8
-
+0.6
0.9
1.1
0.4
0.6
-0.8
+0.8
0.75
1.25
0
0.25
0.4
0.6
0.4
0.6
0.9
1.1
1.1
1.1
16
0.6
0.6
2
10
116
Unit Note
ns
ns
ns
ns
ns
ns
tCK
tCK
tCK
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
ns 2
tCK
ns 3
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
- 44 -
REV. 1.0 November. 2. 2000