K4H280438B-TCA0 Datasheet, PDF (43/53 Pages) Samsung semiconductor – 128Mb DDR SDRAM

128Mb DDR SDRAM
IDD7 : Operating current: Four bank operation
1. Typical Case : Vdd = 2.5V, T=25’C
2. Worst Case : Vdd = 2.7V, T= 10’C
3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
8. AC Operating Conditions & Timming Specification
8.1 AC Operating Conditions
Parameter/Condition
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
Symbol
Min
Max
Unit
VIH(AC) VREF + 0.31
V
VIL(AC)
VREF - 0.31
V
VID(AC) 0.62
VDDQ+0.6
V
VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2
V
Note
1
2
3
4
Note 1. Vih(max) = 4.2V. The overshoot voltage duration is ≤ 3ns at VDD.
2. Vil(min) = -1.5V. The undershoot voltage duration is ≤ 3ns at VSS.
3. VID is the magnitude of the difference between the input level on CK and the input on CK.
4. The value of V_IX is expected to equal 0.5*V_DDQ of the transmitting device and must track variations in the DC level of the same.
Table 13. AC operating conditions
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REV. 1.0 November. 2. 2000