K4H280438B-TCA0 Datasheet, PDF (24/53 Pages) Samsung semiconductor – 128Mb DDR SDRAM

128Mb DDR SDRAM
3.3.6 Write Interrupted by a Write
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restric-
tion that the interval that separates the commands must be at least one clock cycle. When the previous burst
is interrupted, the remaining addresses are overridden by the new address and data will be written into the
device until the programmed burst length is satisfied.
< Burst Length=4 >
0
CK
CK
Command NOP
1
2
1tCK
WRITE A WRITE b
3
NOP
4
NOP
5
NOP
6
NOP
7
NOP
8
NOP
DQS
DQ ′s
Din A0 Din A1 Din B0 Din B1 Din B2 Din B3
Figure 14. Write interrupted by a write timing
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REV. 1.0 November. 2. 2000