K4H280438B-TCA0 Datasheet, PDF (46/53 Pages) Samsung semiconductor – 128Mb DDR SDRAM

128Mb DDR SDRAM
9. AC Operating Test Conditions
(VDD=2.5V, VDDQ=2.5V, TA= 0 to 70°C)
Parameter
Input reference voltage for Clock
Input signal maximum peak swing
Input signal minimum slew rate
Input Levels(VIH/VIL)
Input timing measurement reference level
Output timing measurement reference level
Output load condition
Value
0.5 * VDDQ
1.5
1.0
VREF+0.31/VREF-0.31
VREF
Vtt
See Load Circuit
Table 15. AC operating test conditions
Vtt=0.5*VDDQ
Output
RT=50Ω
Z0=50Ω
CLOAD=30pF
VREF
=0.5*VDDQ
Unit
V
V
V/ns
V
V
V
Note
Figure 24. Output Load Circuit (SSTL_2)
10. Input/Output Capacitance
(VDD=2.5, VDDQ=2.5V, TA= 25°C, f=1MHz)
Parameter
Symbol Min
Input capacitance
(A0 ~ A11, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)
CIN1
2
Input capacitance( CK, CK )
CIN2
2
Data & DQS input/output capacitance
COUT
4.0
Input capacitance(DM)
CIN3
4.0
Max Delta Cap(max) Unit
3.0
0.5
pF
3.0
0.25
pF
5.0
pF
0.5
5.0
pF
Table 16. Input/output capacitance
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REV. 1.0 November. 2. 2000