K4S641632C Datasheet, PDF (5/42 Pages) Samsung semiconductor – 1M x 16Bit x 4 Banks Synchronous DRAM

K4S641632C
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
3.3V
Output
870Ω
1200Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
50pF^*Note1
Output
CMOS SDRAM
Unit
V
V
ns
V
Z0 = 50Ω
Vtt = 1.4V
50Ω
50pF^*Note1
(Fig. 1) DC output load circuit
Note : 1. The DC/AC test Output Load of K4S641632C-60 is 30pF.
2. The VDD condition of K4S641632C-60 is 3.135V~3.6V.
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
-60
-70
Version
-75
-80
-1H
-1L
-10
Unit
Not
e
Row active to row active delay
tRRD(min) 12
14
14
16
20
20
20
ns
1
RAS to CAS delay
tRCD(min) 18
20
20
20
20
20
24
ns
1
Row precharge time
tRP(min)
18
20
20
20
20
20
24
ns
1
Row active time
tRAS(min)
42
48
48
48
50
50
50
ns
1
tRAS(max)
100
us
Row cycle time
tRC(min)
60
68
68
68
70
70
80
ns
1
Last data in to row precharge
tRDL(min)
6
7
7
8
10
10
12
ns
2
Last data in to new col. address Delay tCDL(min)
1
CLK 2
Last data in to burst stop
tBDL(min)
1
CLK 2
Col. address to col. address delay
tCCD(min)
1
CLK 3
Number of valid output
data
CAS latency=3
CAS latency=2
2
ea
4
1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.