K4S641632C Datasheet, PDF (26/42 Pages) Samsung semiconductor – 1M x 16Bit x 4 Banks Synchronous DRAM

K4S641632C
CMOS SDRAM
*Note : 1. All input except CKE & DQM can be don't care when CS is high at the CLK high going edge.
2. Bank active & read/write are controlled by BA0~BA1.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
BA0 BA1
Active & Read/Write
00
Bank A
01
Bank B
10
11
Bank C
Bank D
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command
A10/AP BA0 BA1
Operation
0 0 Disable auto precharge, leave bank A active at end of burst.
0 1 Disable auto precharge, leave bank B active at end of burst.
0
1 0 Disable auto precharge, leave bank C active at end of burst.
1 1 Disable auto precharge, leave bank D active at end of burst.
0 0 Enable auto precharge, precharge bank A at end of burst.
0 1 Enable auto precharge, precharge bank B at end of burst.
1
1 0 Enable auto precharge, precharge bank C at end of burst.
1 1 Enable auto precharge, precharge bank D at end of burst.
4. A10/AP and BA0~BA1 control bank precharge when precharge command is asserted.
A10/AP BA0 BA1
0
00
0
01
0
10
0
11
1
xx
Precharge
Bank A
Bank B
Bank C
Bank D
All Banks
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