K4S641632C Datasheet, PDF (30/42 Pages) Samsung semiconductor – 1M x 16Bit x 4 Banks Synchronous DRAM

K4S641632C
Page Read Cycle at Different Bank @Burst Length=4
CMOS SDRAM
CLOCK
CKE
CS
01
*Note 1
23
45
67
8 9 10 11 12 13 14 15 16 17 18 19
HIGH
RAS
CAS
*Note 2
ADDR
RAa
RBb CAa
RCc CBb
RDd CCc
CDd
BA0
BA1
A10/AP
RAa
RBb
RCc
RDd
CL=2
DQ
CL=3
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Row Active
(B-Bank)
Read
(B-Bank)
Read
(C-Bank)
Row Acive
(C-Bank)
Row Active
(D-Bank)
Precharge
(A-Bank)
Precharge
(B-Bank)
Read
(D-Bank)
Precharge
(D-Bank)
Precharge
(C-Bank)
*Note : 1. CS can be don't cared when RAS, CAS and WE are high at the clock high going dege.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
: Don't care
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