K4S641632C Datasheet, PDF (18/42 Pages) Samsung semiconductor – 1M x 16Bit x 4 Banks Synchronous DRAM

K4S641632C
CMOS SDRAM
5. Write Interrupted by Precharge & DQM
CLK
CMD
DQM
DQ
WR
Note 3
PRE
Note 2
D0 D1 D2 D3
Masked by DQM
*Note : 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
interrupt but only another bank precharge of four banks operation.
6. Precharge
1) Normal Write (BL=4)
CLK
CMD
DQ
WR
PRE
D0 D1 D2 D3
tRDL
Note 2
2) Normal Read (BL=4)
CLK
CMD
RD
DQ(CL2)
DQ(CL3)
PRE
1
Q0 Q1 Q2 Q3
2
Q0 Q1 Q2 Q3
7. Auto Precharge
1) Normal Write (BL=4)
CLK
CMD
DQ
WR
D0 D1 D2 D3
Note 3
Auto Precharge Starts
2) Normal Read (BL=4)
CLK
CMD
RD
DQ(CL2)
DQ(CL3)
*Note : 1. tRDL : Last data in to row precharge delay
2. Number of valid output data after row precharge : 1, 2 for CAS Latency = 2, 3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
D0 D1 D2 D3
D0 D1 D2 D3
Note 3
Auto Precharge Starts
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