K4S641632C Datasheet, PDF (20/42 Pages) Samsung semiconductor – 1M x 16Bit x 4 Banks Synchronous DRAM

K4S641632C
10. Clock Suspend Exit & Power Down Exit
1) Clock Suspend (=Active Power Down) Exit
CLK
CKE
Internal
CLK
CMD
Note 1
tSS
RD
CMOS SDRAM
2) Power Down (=Precharge Power Down)
CLK
CKE
Internal
CLK
CMD
Note 2
tSS
NOP ACT
11. Auto Refresh & Self Refresh
1) Auto Refresh & Self Refresh Note 3
CLK
CMD
Note 4
PRE
AR
CKE
tRP
2) Self Refresh Note 6
CLK
CMD
Note 4
PRE
SR
CKE
tRP
¡ó
¡ó
¡ó
¡ó
tRC
Note 5
CMD
¡ó
CMD
¡ó
¡ó
tRC
*Note : 1. Active power down : one or more banks active state.
2. Precharge power down : all banks precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after auto refresh command.
During tRC from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, all banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh mode, refresh interval and refresh operation are perfomed internally.
After self refresh entry, self refresh mode is kept while CKE is low.
During self refresh mode, all inputs except CKE will be don't cared, and outputs will be in Hi-Z state.
For the time interval of tRC from self refresh exit command, any other command can not be accepted.
Before/After self refresh mode, burst auto refresh cycle (4096 cycles) is recommended.
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