K4S641632C Datasheet, PDF (32/42 Pages) Samsung semiconductor – 1M x 16Bit x 4 Banks Synchronous DRAM

K4S641632C
Read & Write Cycle at Different Bank @Burst Length=4
CMOS SDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CS
RAS
CAS
ADDR
RAa
CAa
RDb
CDb RBc
CBc
BA0
BA1
A10/AP
RAa
CL=2
DQ
CL=3
RBb
QAa0 QAa1 QAa2 QAa3
QAa0 QAa1 QAa2 QAa3
RAc
*Note 1
tCDL
DDb0 DDb1 DDb2 DDb3
QBc0 QBc1 QBc2
DDb0 DDb1 DDb2 DDb3
QBc0 QBc1
WE
DQM
Row Active Read
(A-Bank) (A-Bank)
Precharge
(A-Bank)
Row Active
(D-Bank)
Write
(D-Bank)
Precharge
(B-Bank)
Read
(B-Bank)
: Don't care
*Note : 1. tCDL should be met to complete write.
ELECTRONICS