K4S641632C Datasheet, PDF (35/42 Pages) Samsung semiconductor – 1M x 16Bit x 4 Banks Synchronous DRAM

K4S641632C
Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4
CMOS SDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cb
Cc
BA0
BA1
A10/AP
Ra
DQ
WE
DQM
Qa0 Qa1
Qa2
Qa3
tSHZ
Qb0 Qb1
Dc0
Dc2
tSHZ
*Note 1
Row Active Read
Clock
Suspension
*Note : 1. DQM is needed to prevent bus contention.
Read
Read DQM
Write
DQM
Write
Clock
Suspension
Write
DQM
: Don't care
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