K4T1G164QE-HCE7000 Datasheet, PDF (43/46 Pages) Samsung semiconductor – 1Gb E-die DDR2 SDRAM 60FBGA/84FBGA with Lead-Free & Halogen-Free (RoHS compliant)

K4T1G044QE
K4T1G084QE
K4T1G164QE
datasheet
Rev. 1.12
DDR2 SDRAM
24. tWTR is at lease two clocks (2 x tCK or 2 x nCK) independent of operation frequency.
25. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the V_IH(AC) level to the sin-
gle-ended data strobe crossing V_IH/L(DC) at the start of its transition for a rising signal, and from the input signal crossing at the V_IL(AC) level to the
single-ended data strobe crossing V_IH/L(DC) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be
monotonic between V_IL(DC)max and V_IH(DC)min.
26. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the V_IH(DC) level to the
single-ended data strobe crossing V_IH/L(AC) at the end of its transition for a rising signal, and from the input signal crossing at the V_IL(DC) level to the
single-ended data strobe crossing V_IH/L(AC) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be
monotonic between V_IL(DC)max and V_IH(DC)min.
27. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire
time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of
tIS + 2 x tCK + tIH.
28. If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
29. These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective
clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and
hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is pres-
ent or not.
30. These parameters are measured from a data strobe signal ((L/U/R)DQS/DQS) crossing to its respective clock signal (CK/CK) crossing. The spec val-
ues are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these
parameters should be met whether clock jitter is present or not.
31. These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/
R)DQS/DQS) crossing.
32. For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK(avg)}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied.
For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For
DDR2-667 5-5-5, of which tRP = 15ns, the device will support tnRP = RU{tRP / tCK(avg)} = 5, i.e. as long as the input clock jitter specifications are
met, Precharge command at Tm and Active command at Tm+5 is valid even if (Tm+5 - Tm) is less than 15ns due to input clock jitter.
33. tDAL [nCK] = WR [nCK] + tnRP [nCK] = WR + RU {tRP [ps] / tCK(avg) [ps] }, where WR is the value programmed in the mode register set.
34. New units, ’tCK(avg)’ and ’nCK’, are introduced in DDR2-667 and DDR2-800. Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under
operation. Unit ’nCK’ represents one clock cycle of the input clock, counting the actual clock edges.
Note that in DDR2-400 and DDR2-533, ’tCK’ is used for both concepts.
ex) tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm+2, even if (Tm+2 - Tm) is 2 x tCK(avg)
+ tERR(2per),min.
35. Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec parameters' and these
parameters apply to DDR2-667 and DDR2-800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
Parameter
Symbol
DDR2-667
Min
Max
DDR2-800
Min
Max
units NOTE
Clock period jitter
tJIT(per)
-125
125
-100
100
ps
35
Clock period jitter during DLL locking period
tJIT(per,lck)
-100
100
-80
80
ps
35
Cycle to cycle clock period jitter
tJIT(cc)
-250
250
-200
200
ps
35
Cycle to cycle clock period jitter during DLL locking period
tJIT(cc,lck)
-200
200
-160
160
ps
35
Cumulative error across 2 cycles
tERR(2per)
-175
175
-150
150
ps
35
Cumulative error across 3 cycles
tERR(3per)
-225
225
-175
175
ps
35
Cumulative error across 4 cycles
tERR(4per)
-250
250
-200
200
ps
35
Cumulative error across 5 cycles
tERR(5per)
-250
250
-200
200
ps
35
Cumulative error across n cycles, n = 6 ... 10, inclusive
tERR(6-10per)
-350
350
-300
300
ps
35
Cumulative error across n cycles, n = 11 ... 50, inclusive tERR(11-50per) -450
450
-450
450
ps
35
Duty cycle jitter
tJIT(duty)
-125
125
-100
100
ps
35
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