K4T1G164QE-HCE7000 Datasheet, PDF (4/46 Pages) Samsung semiconductor – 1Gb E-die DDR2 SDRAM 60FBGA/84FBGA with Lead-Free & Halogen-Free (RoHS compliant)

K4T1G044QE
K4T1G084QE
K4T1G164QE
datasheet
1. Ordering Information
Organization
256Mx4
128Mx8
64Mx16
DDR2-800 5-5-5
K4T1G044QE-HC(L)E7
K4T1G084QE-HC(L)E7
K4T1G164QE-HC(L)E7
DDR2-800 6-6-6
K4T1G044QE-HC(L)F7
K4T1G084QE-HC(L)F7
K4T1G164QE-HC(L)F7
NOTE :
1. Speed bin is in order of CL-tRCD-tRP.
2. RoHS Compliant.
3. “H” of Part number(12th digit) stands for Lead-Free, Halogen-Free, and RoHS compliant products.
4. “C” of Part number(13th digit) stands normal, and “L” stands for Low power products.
Rev. 1.12
DDR2 SDRAM
DDR2-667 5-5-5
K4T1G044QE-HC(L)E6
K4T1G084QE-HC(L)E6
K4T1G164QE-HC(L)E6
Package
60 FBGA
60 FBGA
84 FBGA
2. Key Features
Speed
CAS Latency
tRCD(min)
tRP(min)
tRC(min)
DDR2-800 5-5-5
5
12.5
12.5
57.5
DDR2-800 6-6-6
6
15
15
60
DDR2-667 5-5-5
5
15
15
60
Units
tCK
ns
ns
ns
• JEDEC standard V_DD = 1.8V ± 0.1V Power Supply
• V_DDQ = 1.8V ± 0.1V
• 333MHz f_CK for 667Mb/sec/pin, 400MHz f_CK for 800Mb/sec/pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5, 6
• Programmable Additive Latenc y: 0, 1, 2, 3, 4, 5
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an
optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Special Function Support
- 50ohm ODT
- High Temperature Self-Refresh rate enable
The 1Gb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 8banks, 16Mbit
x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks device. This synchronous
device achieves high speed double-data-rate transfer rates of up to 800Mb/
sec/pin (DDR2-800) for general applications.
The chip is designed to comply with the following key DDR2 SDRAM fea-
tures such as posted CAS with additive latency, write latency = read latency
- 1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. For example, 1Gb(x8) device
receive 14/10/3 addressing.
The 1Gb DDR2 device operates with a single 1.8V ± 0.1V power supply
and 1.8V ± 0.1V V_DDQ.
The 1Gb DDR2 device is available in 60ball FBGA(x4/x8) and in 84ball
FBGA(x16).
• Average Refresh Period 7.8us at lower than T_CASE 85°C, 3.9us at
85°C < T_CASE < 95 °C
• All of products are Lead-Free, Halogen-Free, and RoHS compliant
NOTE :
1. This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “DDR2 SDRAM Device Operation & Timing Dia-
gram”.
2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
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