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| K4T1G164QE-HCE7000 Datasheet, PDF (30/46 Pages) Samsung semiconductor – 1Gb E-die DDR2 SDRAM 60FBGA/84FBGA with Lead-Free & Halogen-Free (RoHS compliant) | |||
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K4T1G044QE
K4T1G084QE
K4T1G164QE
datasheet
Rev. 1.12
DDR2 SDRAM
DQS
Note1
VDDQ
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
VSS
VDDQ
VIH(AC)min
VREF to ac
region
VIH(DC)min
VREF(DC)
tDS tDH
nominal
line
tangent
line
tDS tDH
tangent
line
VIL(DC)max
VIL(AC)max
nominal
line
VSS
âTF
VREF to ac
region
âTR
Setup Slew Rate tangent line[VIH(AC)min - VREF(DC)]
Rising Signal=
âTR
Setup Slew Rate tangent line[VREF(DC) - VIL(AC)max]
Falling Signal =
âTF
NOTE : DQS signal must be monotonic between VIL(DC)max and VIH(DC)min.
Figure 10. IIIustration of tangent line for tDS (single-ended DQS)
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